1. Field of the Invention
The present invention relates to a semiconductor integrated circuit design supporting apparatus, method, and program for supporting design of a semiconductor integrated circuit, which utilizes high level synthesis or behavioral synthesis of automatically generating, based on a behavioral description of a circuit, a register transfer level (RTL) description for the semiconductor integrated circuit.
2. Description of the Related Art
Hitherto, a semiconductor integrated circuit has been designed with use of hardware description language (HDL) by RTL, which describes the behavior of combinational logic between registers (flip-flops) included in a circuit. In recent years, integrated circuits have become larger in scale, which has caused a problem in that a large amount of time is required in RTL design. In view of this, there has been proposed a technology of automatically generating an RTL description with use of high level languages such as C language, C++ language, and SystemC language, which have higher level of abstraction than that of RTL. A high level synthesis tool for realizing this technology is available.
On the other hand, there has been proposed an auxiliary design technology for realizing processing that cannot be realized by the high level synthesis tool alone. Japanese Patent Application Laid-open No. 2010-165334 (Patent Literature 1) discloses a configuration in which, in order to adjust the latency between a plurality of modules, the number of stages of flip-flops (FFs) of the modules is extracted, and then an FF is automatically inserted between the modules. Thus, the latency between the plurality of modules can be automatically adjusted.
However, the object of Patent Literature 1 is to automatically adjust the latency. Therefore, there arises a problem in that, as the entire circuit, the inserted FF is not located at an optimum position from the viewpoint of circuit scale and entire processing performance.
The case where the above-mentioned inserted FF is not located at an optimum position is considered with reference to an example of FIG. 31. FIG. 31 illustrates an example in which Module A and Module B are connected to Module C, and two FFs are inserted between Module B and Module C by the method of Patent Literature 1. Patent Literature 1 discloses that the design may be efficiently performed by extracting the latency of each module, and automatically inserting an FF for latency adjustment between the modules.
FIG. 32 illustrates an example of details inside Module C of FIG. 31. The key point is that Module C receives an input of a pin a1 by an FF. In this case, the FF inserted between Module B and Module C and the FF that is provided inside Module C and receives the input of the pin a1 may cancel each other out, and hence the number of FFs to be inserted between Module B and Module C can be reduced to one as illustrated in FIG. 33.
Another example is described. FIG. 34 is a simplified view illustrating an internal configuration and FFs of Module B. Module B performs arbitrary calculation based on a 10-bit input, and temporarily stores the calculation result by an FF of 8 bits. The result is further subjected to calculation processing, and is output by an FF of (8 bits)×2. The output of the FF of (8 bits)×2 is connected to Module C. Therefore, in this related art, when the bits of Module B and the inserted FFs are added, FFs of 56 bits are inserted, as represented by the expression in FIG. 35.
On the other hand, if it is possible to insert the FFs at positions in Module B, which have a small number of FF bits, as illustrated in FIG. 36 instead of positions between Module B and Module C, the total FFs can be reduced to 40 bits, as represented by the expression in FIG. 37.
As described above, in view of the entire circuit, the FFs inserted between the modules disclosed in Patent Literature 1 may not be located at optimum positions in terms of circuit scale.